T1/E1 Basic Bit Error Rate Test
T1/E1 Basic Bit Error Rate Test
Overview
The Bit Error Rate Test (BERT) application generates/detects unframed, framed, and fractional data that are defined in Pseudo Random Bit Sequence (PRBS). In addition to these, drop and insert capability is provided. A variety of standard data patterns are available for test purposes including static and user selected patterns.
To open BER application, navigate to T1/E1 Analyzer > Intrusive Test > Bit Error Rate Test. Select the card on which BER test has to be performed. The screenshot given above displays the BER test application running on Card1:
The functionality of the PRBS data stream is illustrated in the figure below:
Framing Patterns selection for T1/E1
The framing patterns available in BER test are Unframed, Full-Framed, Fractional without Drop and Insert (D&I) and Fractional with Drop and Insert modes. These can be selected from the drop-down menu in the "Full-Fractional-Unframe" section.
- Unframed T1/E1: Entire T1/E1 bit rate is used to transmit /receive the selected pattern. In T1, the framing bit position is used for pattern data and not for framing bits. In E1, timeslot 0 is used for pattern data and not for framing bits.
- Full Framed T1/E1: The selected pattern is inserted such that all 24/31 timeslots are used. In T1, the framing bit position is used for the normal framing bits. In E1, timeslot 0 is used for normal framing bits.
- Fractional T1/E1 with Drop and Insert: The selected T1/E1 timeslots are dropped and the user-selected pattern is inserted into the selected T1/E1 timeslots. The selected timeslots must be contiguous and cannot wrap around the last timeslot. The unselected T1/E1 timeslots are passed through undisturbed. The Drop and Insert function preserves multiframe alignment in all framing formats.
- Fractional T1/E1 without Drop and Insert: The user selected T1/E1 timeslots are used to transmit/receive the selected pattern. The selected timeslots must be contiguous and cannot wrap around the timeslot 23/31. The data in the remaining channels is taken from the timeslots in memory.
Pattern selection for T1/E1
BERT application has various available data patterns as explained in the table below :
| BER Pattern | Description |
|---|---|
| Quasi Random Signal Source (QRSS) | Quasi-random signal source (QRSS) is a modified version of the PRBS (Pseudo Random Bit Sequence) and 20 consecutive ones permitted. The length of this pattern is 1,048,575 bits. This pattern is generally used as a test signal to test T1 lines. |
| 2ˆ6-1 (63) | This is Pseudo Random Bit Sequence (PRBS) generated by six (6)-stage shift register. Here a maximum of five consecutive zeros and consecutive ones are generated. The length of this pattern is 63 bits. |
| 2ˆ9-1 (511) | This is PRBS generated by nine (9)-stage shift register. Here a maximum of eight consecutive zeros and nine consecutive ones is generated. The length of this pattern is 511 bits. |
| 2ˆ11-1 (2047) | This is PRBS generated by eleven (11)-stage shift register. Here a maximum of ten consecutive zeros and eleven consecutive ones is generated. The length of this pattern is 2047 bits. |
| 2ˆ15-1 | This is PRBS generated by fifteen (15)-stage shift register. Here a maximum of 14 consecutive zeros and 15 consecutive ones is generated. The Length of this pattern is 32,767 bits. |
| 2ˆ20-1 | This is PRBS generated by twenty (20)-stage shift register. Here a maximum of 19 consecutive zeros and 20 consecutive ones is generated. The length of this pattern is 1,048,575 bits. See definition of QRSS. |
| 2ˆ23-1 | This is PRBS generated by twenty-three (23)-stage shift register. Here a maximum of 22 consecutive zeros and 23 consecutive ones is generated. The length of this pattern is 8,388,607 bits. |
| CSU (Channel Service Unit) Loop Up Code | This code may be transmitted in unframed or framed mode, but should not be used in the fractional mode. The framed sequence consists of a repetitive 5 bit sequence "00001" with the framing bit in its normal position. The unframed sequence consists of the same repetitive 5bit sequence without a framing bit. The CSU Loop Up Code operation is as follows: When Unit A transmits this code towards Unit B, it recognizes it and effects a loop on the entire signal back towards Unit A. Unit A upon detecting the returned signal declares "PatSync", which is indicative of a signal loop in the system. Once this condition is established, the user of Unit A may perform BER testing and other tests on the looped signal. To unestablish the loop, Unit A must transmit the CSU Loop Down Code towards the remote end. |
| CSU Loop Down Code | This code may be transmitted in unframed or framed mode, but should not be used in the fractional mode. The CSU Loop Down Code is a 3 bit sequence "001" and is similar to the CSU Loop Up Code in the unframed and framed modes. The CSU Loop Down Code operation is as follows. When Unit A transmits this code towards Unit B ,it unestablishes a loop, if present. Unit A upon detecting the absence of the CSU Loop Down Code declares "No Sync", which indicates that the loop is no longer in the system. Enabling the Network Loopback Detection option in the Config dropdown menu sets the analyzer to detect the CSU Loop Up and CSU Loop Down Codes. If enabled, for about five seconds the Loop Up and Loop Down Codes are detected. The detection is performed for Framed CSU Loop Up/Down Codes and Unframed CSU Loop Up/Down Codes. The detection is also performed on Framed CSU Loop Up/Down Codes in which the framing bit overwrites an Unframed CSU Loop Up/Down Code. |
| NIU Loop UP and Loop Down codes | NIU loop Up/Down code is used, when the user wants to test from CO (Central office) out to a NIU (Network Interface Unit). Loop up code is of 5 bits ('11000' as defined in application) and Loop down code is of 3 bits (111). These are the repetitive sequences which are transmitted to establish and unestablish the loop for BERT testing. |
| All Ones | It's a Static pattern of continuous ones. |
| All Zeros | It's a Static pattern of continuous zeros. For T1 systems the line code should be set for B8ZS when using this pattern. |
| 1:1 | It's a Static pattern of alternating ones and zeros. |
| 1:7 | It's a Static pattern with one "1" and seven "0"s. |
| 3 in 24 | It's a Static pattern with three "1"s in a string of 24 bits User Defined User definable 24-bit static pattern. |
BER Test Result Screen
- Frame Errors Statistics Column: Lists frame error statistics
- Bipolar Violations Statistics Column: Lists bipolar violation statistics
- Logic Errors Statistics Column: Lists all logic error statistics
- Status/Errors: "Pat Sync" is displayed in this field if BER is less than 0.019. "No Pulses" is displayed if no signal is received.
- Total Bit Errors: This is the Count of total number of bit errors detected after Pat Sync is achieved.
- Err Rate (Cont): This is the ratio of Total Bit Errors to the total number of bits received i.e., the BER.
- Err Second (ES): It is the number of seconds with one or more errors detected during the Pat Sync condition.
- Err Free Second (EFS): It is the number of seconds with no errors detected during the Pat Sync condition.
- %EFS: The ratio of EFS to Test Sec multiplied by 100, where, Test Sec = Test Run Sec - Loss of Pat Sync Sec.
- Severely Err Sec (SES): It is the number of Test Sec with a Bit Error Rate worse than 1*10-3 in each second.
- %SES: This is the ratio of SES to Test Sec multiplied by 100.
- Degraded Minutes: The number minutes with a Bit Error Rate in each minute equal to or worse than 1.0*10-6
- %Dmin: This is the ratio of Degraded Minutes to the Test Run Minutes. Loss of Pat Sync time is included in Test Run Minutes.
- Loss of Sync Count: The count of number of times the pattern sync was lost. Pat Sync is automatically re-established if lost.
- Loss of Sync Sec: The total number of seconds the pattern sync was lost. If Pat Sync was momentarily lost and re-established during 1-second interval (one or more times), then this count is incremented by one.
- Available Seconds: The number of seconds with a BER in each second better than .0*10-3
- %Available Sec: It is the ratio of available seconds to the Test Run Sec multiplied by 100. Loss of Pat Sync time is included in Test Run Sec.
- Unavailable Seconds: It is the number of seconds with a BER in each second worse than 1.0*10-3. The count begins at ten and after ten consecutive unavailable seconds has been detected.
- Insert Single Logic Error, Insert BPV: <Alt+E> Logic - This key is used to insert a single logic error. <Alt+B> BPV - This key is used to insert single shot BPV errors.
BER Logging and DS0 Settings
BER LoggingSelect the enable box to log all test events continuously. Test results are logged to an ASCII file. All the events displayed are logged to the ASCII file.
An example of a logged file is as shown below:
Thu Oct 21 14:47:05 1999, LEQRSS.BIN, FRAMED, NO_DATAINV, NO_D&I, 1, 31
Thu Oct 21 14:47:05 1999, RESTART
Thu Oct 21 14:47:05 1999, PATSYNC
Thu Oct 21 14:47:14 1999, LOGIC_ERROR, 374
Thu Oct 21 14:47:15 1999, ERRORED_SECOND
Thu Oct 21 14:47:15 1999, LOGIC_ERROR, 95
Thu Oct 21 14:47:20 1999, LOGIC_ERROR, 659
Thu Oct 21 14:47:20 1999, BPV_ERROR, 1234
Thu Oct 21 14:47:21 1999, ERRORED_SECOND
Thu Oct 21 14:47:21 1999, LOGIC_ERROR, 35
Thu Oct 21 14:47:21 1999, BPV_ERROR, 90
Thu Oct 21 14:47:24 1999, STATUS, PATSYNC
Thu Oct 21 14:47:24 1999, TOTAL_LOGIC_ERRORS, 1163
Thu Oct 21 14:47:24 1999, TOTAL_LOGIC_ERROR_RATE, 3.19E-005
Thu Oct 21 14:47:24 1999, TOTAL_LOGIC_ERRORED_SECONDS, 2
Thu Oct 21 14:47:24 1999, TOTAL_LOGIC_ERROR_FREE_SECONDS, 17
Thu Oct 21 14:47:24 1999, TOTAL_LOGIC_ERROR_FREE_SECONDS_PERCENT, 89.47
Thu Oct 21 14:47:24 1999, TOTAL_SEVERELY_ERRORED_SECONDS, 0
Thu Oct 21 14:47:24 1999, TOTAL_SEVERELY_ERRORED_SECONDS_PERCENT, 0.00
Thu Oct 21 14:47:24 1999, TOTAL_DEGRADED_MINUTES, 0
Thu Oct 21 14:47:24 1999, TOTAL_DEGRADED_MINUTES_PERCENT, 0.00
Thu Oct 21 14:47:24 1999, TOTAL_LOSS_OF_SYNC_COUNT, 0
Thu Oct 21 14:47:24 1999, TOTAL_LOSS_OF_SYNC_SECONDS, 0
Thu Oct 21 14:47:24 1999, TOTAL_AVAILABLE_SECONDS, 19
Thu Oct 21 14:47:24 1999, TOTAL_AVAILABLE_SECONDS_PERCENT, 100.00
Thu Oct 21 14:47:24 1999, UNAVAILABLE_SECONDS, 0
Thu Oct 21 14:47:24 1999, TOTAL_BPV_ERRORS, 1324
Thu Oct 21 14:47:24 1999, TOTAL_BPV_ERROR_RATE, 3.63E-005
Thu Oct 21 14:47:24 1999, TOTAL_BPV_ERRORED_SECONDS, 1
Thu Oct 21 14:47:24 1999, TOTAL_BPV_ERROR_FREE_SECONDS, 18
Thu Oct 21 14:47:24 1999, EXIT
DS0 Data Rate (56/64) - T1 Systems Only
By checking the "56/64K" control, it is possible to place the T1 card in 56 Kbps mode.
Example:
Cross Connect port1 and port2 of T1/E1 cards and invoke the Bit Error Rate software under intrusive Test for both cards.
In the Full-Fractional- Unframe drop-down menu, select to test the 'Full Frame' by observing whether it has No Errors or Loss of sync status. When Testing the unframed, users can notice the Loss of Sync and frame errors and this is normal. Note that inserting random errors and bipolar violations (BPV) features are used for testing purpose. The total errors count will increase as you insert the errors.
Check the Frame Error alarm on the Monitor dialog box after inserting BPV.
Comparison with other GL's BERT Applications
MCBERT
- Supports both real-time and offline analysis. In real-time, data along with pattern file is transmitted on timeslots and sub-channels for analysis. In offline, the stored data file is loaded and compared with the pattern file
- Patterns files are externally loaded
- Provides results in tabular format and logs results in *.txt files
- Supports sub-channels 01, 02, 04, 08, 10, 20, 40, 80
For more information, please visit Multi-channel BERT page
Enhanced BERT
- Supports real-time generation of patterns, and errors (Logic error, BPV) on framed, unframed, and fractional
- Send/Receive BER pattern with Tx and Rx settings coupled or independently controlled. Supports multiple cards simultaneously with consolidated result view
- Supports sub-channels from 00 to FF along with contiguous & non-contiguous timeslot selections
- Supports both real-time and offline analysis of events graphically and in tabular formats
- Supports 16-static patterns as well as user-defined bit patterns
- Supports predefined and user-defined error insertions ranging from 0.01 to 1e-009
- Analysis and logs results in *.xml files
For more information, please visit Enhanced BERT page
